This invention relates generally to an integrated circuit having at least two vertically stacked semiconductor substrates, and more specifically to TSV (through substrate via) structures formed in such an integrated circuit.
Integrated circuits have become ubiquitous. Today ‘complimentary metal on semiconductor’ (CMOS) technology can create billions of devices such as transistors for logic or memory (or both) on a single semiconductor substrate; which single substrate is known as a ‘monolithic integrated circuit’ and will be referred to herein as a chip. Hundreds of chips can be formed together as regions of a single semiconductor wafer and then diced to separate the individual chips. The devices are formed on a ‘front-side’ surface of a wafer by so-called ‘front end of the line’ processing (FEOL) of a wafer, with wafer processing typically continuing to form a contact layer (so called ‘middle of the line’ or MOL) and wiring to interconnect the devices of the single substrate (so-called ‘back end of the line’ or BEOL) before the wafer is diced.
In order to continue to improve performance and functionality of integrated circuits, the industry has recently been developing technology to vertically integrate two or more chips into a single vertically integrated component. In some embodiments, the two or more chips can each have active semiconductor devices (such as field effect transistors). In other embodiments, at least one of such two or more chips can be an ‘interposer’ which may not have any semiconductor devices or might only have passive semiconductor devices (such as a capacitor). Whereas the ‘monolithic IC’ includes a single semiconductor substrate (but could have other structural layers such as an organic laminate packaging), the single vertically integrated component is referred to herein as a three-dimensional (3D) integrated circuit (3D IC). A 3D IC includes at least two chips stacked together (and could similarly have additional layers such as a packaging laminate). Like the monolithic IC, many 3D ICs can theoretically be formed simultaneously by bonding entire (or partial) wafers and then singulating the individual 3D ICs by dicing the stack, each 3D IC having two or more chips vertically bonded together.
Whereas the device face (front-side) of a single chip IC can be directly against the packaging structure which delivers power and carries signals between the chip and the outside world, the 3D IC has at least one chip that is separated from the packaging by another chip. Power can be delivered to the devices of the at least one remote chip or devices on different chips of the same 3D IC can be interconnected using conductive elements that extend entirely through intermediate chips, referred to as ‘through substrate vias’ (TSVs). Put another way, a TSV is a conductive path within a 3D IC that passes through a chip and conductively connects elements located on opposite sides of that chip. A 3D IC can theoretically include any number of chips (C1, C2, . . . Cx, x>=2) and a TSV can theoretically connect any one chip of the stack to any other chip of the stack or to the packaging interface by passing through the one or more chips in between (e.g., if x=4, C1 can be connected to C4 by a TSV that passes through C2 and C3).
The intermediate substrates must be thinned to enable forming TSVs. TSVs can be formed into the substrate during fabrication of the front side, for example by etching a TSV cavity into a substrate, forming an insulating layer, depositing barrier and seed layers, plating to fill the cavity (which can be achieved by bottom-up techniques to avoid forming voids in the very high aspect ratio TSV cavity), CMP (chemical mechanical planarization), and building interconnects to connect to the TSV in a subsequent BEOL level. In such a flow scheme, the back side of the substrate can subsequently be thinned to expose the remote end of the TSV. Further processing can include cleaning and passivating the grind side.
Semiconductor wafers are produced by growing a single crystalline ingot that is sliced into wafers and polished. Crystal defects, which can agglomerate to form ‘crystal originated particles’ (COPs), and contaminants such as oxygen and metals are inevitably incorporated in the ingot. It is known to form semiconductor devices in a region free of any COPs that have a size larger than or commensurate to the semiconductor devices. One approach is to form a “denuded zone” on the device face of a wafer. For example, US Publ. 2002/0009862 to Mun (hereafter “Mun”) is directed to a two step heat treatment to remove grown-in defects to a required depth (10 to 100 um in claim 11). Another approach disclosed by U.S. Pat. No. 8,231,725 to Sattler et al is to form the crystalline ingot wafer having COP defects with a size not more than 30 nm.
Oxygen and certain other contaminants within the semiconductor ingot are not entirely undesirable since they can form so called precipitates known as ‘bulk micro defects’ (BMD) which can getter metal contaminants. Mun's method also purportedly forms a high density of BMD. U.S. Pat. No. 8,357,939 discloses process conditions to create a denuded zone while retaining a density of BMD above 1e11/cc at depth greater than 50 um and having an equivalent diameter within the range of 10-50 nm.
Additional metal contamination (above and beyond that incorporated during growth of the single crystalline ingot) can be introduced by thinning a wafer such as for incorporation in a 3D IC. U.S. Pat. No. 7,915,145 to Kurita et al discloses to address the additional contamination by careful CMP processing to add ‘extrinsic gettering’ on the grind side of a wafer having an ‘intrinsic gettering’ capability with BMD density in the range of 1e6 to 1e11 and size in the range of 10 to 100 nm.
Before thinning the wafer to expose the TSV, testing is performed to identify (and remove) those chips having flawed circuitry or excessive electrical leakage to the substrate. Electrical leakage can be tested by imposing a high voltage stress, known as ‘time dependent dielectric breakdown’ (TDDB) testing. Many TSVs appear to be structurally sound according to the front side ‘post fab’ testing but apparently contain latent TSV defects which can be triggered by the thinning process because they exhibit unacceptable leakage once the back side has been thinned to expose the TSV. A need remains to reduce the occurrence of such latent flaws within TSVs.